Wafer bonding is the joining together of two or more semiconductor wafers upon which integrated circuitry has been formed to form a three-dimensional wafer stack. The wafer stack is subsequently diced into separate “stacked die,” each stacked die having multiple layers of integrated circuitry. Wafer stacking technology offers a number of potential benefits, including improved form factors, lower costs, enhanced performance, and greater integration through “system-on-chip” solutions. System-on-chip (SOC) architectures formed by wafer stacking can enable high bandwidth connectivity of products—e.g., logic circuitry and dynamic random access memory (DRAM)—that otherwise have incompatible process flows. There are many applications for wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, as well as the above-noted SOC solutions.
An example of a typical wafer stack 100 comprising two bonded wafers is illustrated in FIGS. 1A and 1B. A plan view of the wafer stack is shown in FIG. 1A, and a cross-sectional elevation view is shown in FIG. 1B. Referring to these figures, the wafer stack 100 includes a first wafer 101 and a second wafer 102, each of the wafers 101, 102 comprising a substrate 110, 120, respectively. The substrate 110, 120 of each wafer 101, 102 typically comprises a semiconductor material, such as Silicon (Si), Gallium Arsenide (GaAs), or SiGe. Integrated circuitry for a number of stacked die 105 has been formed on each of the wafers 101, 102, and the wafer stack 100 is ultimately cut into these separate stacked die 105. The integrated circuitry for each stacked die 105 includes a number of active devices 112 (e.g., transistors, capacitors, etc.) formed on the substrate 110 of first wafer 110 and a number of active devices 122 formed on the substrate 120 of second wafer 120.
Disposed over a surface of first wafer 101 is an interconnect structure 114, and disposed over a surface of the second wafer 102 is an interconnect structure 124. Generally, each of the interconnect structures 114, 124 comprises a number of levels of metalization, each layer of metalization separated from adjacent levels by a layer of dielectric material (or other insulating material) and interconnected with the adjacent levels by vias. The dielectric layers of interconnects 114, 124 are often each referred to as an “interlayer dielectric” (or “ILD”). The metalization on each layer comprises a number of conductors (e.g., traces) that may route signal, power, and ground lines to and from the integrated circuitry of each die 105, and this metalization comprises a conductive material, such as Copper or Aluminum. Formed on an uppermost ILD layer of interconnect 114 are conductors 116 and, similarly, formed on an uppermost ILD layer of interconnect 124 are conductors 126. The first and second wafers 101, 102 are bonded together by metal-to-metal bonds between the conductors 116, 126 on their uppermost interconnect layers, respectively. Alternatively, the first and second wafers 101, 102 may be bonded using an adhesive.
Ultimately, the wafer stack 100 will be cut into a number of separate stacked die, as noted above. To couple each stacked die with a next-level component (e.g., a package substrate, a circuit board, a motherboard, another integrated circuit device, a computer system, etc.), a number of leads are provided for each die. For a flip-chip type package—employing, for example, Controlled Collapse Chip Connection (or “C4”) assembly techniques—the number of leads comprises an array of solder balls (or columns). The array of solder balls is electrically coupled with a mating array of leads (e.g., lands, pads, etc.) formed on the next-level component.
Construction of leads on the wafer stack 100 is illustrated in FIG. 1C. The first wafer 101 has been thinned down at a backside 111 of substrate 110, and a layer of dielectric material 150 has been deposited over the substrate's backside surface. A number of vias 113 have also been formed, each of the vias 113 extending through the dielectric layer 150 and wafer substrate 110 and, further, into the interconnect structure 114. A layer of dielectric material 117 (or other insulating material) has been formed on the walls of each via 113, and a conductive material (e.g., Copper) 118 has been deposited within each via 113 over dielectric layer 117. The conductive material 18 in each via 113 extends to one of the ILD layers of interconnect structure 114, where the conductive material forms electrical contact with one of a number of conductors 115 in that ILD layer. Leads 119 (e.g., solder balls or other connection elements) are then deposited on the conductive material 118 at the backside 111 of the first wafer 101, and these connection elements 105 along with conductive material 118 in vias 113 provide electrical connections to a next-level component.
Note that, in FIGS. 1B and 1C, only a limited number of active devices 112, 122, conductors 116, 126, and vias 113 (with conductive material 118 and leads 119) are shown for ease of illustration and clarity. However, those of ordinary skill in the art will appreciate that, in practice, the integrated circuitry associated with each stacked die 105 may include millions or even tens of millions of active devices 112, 122 and, further, that interconnect structures 114, 124 may include tens or even hundreds of conductors 116, 126 in their uppermost ILD layers, respectively. Similarly, those of ordinary skill in the art will appreciate that each stacked die 105 of wafer stack 100 will, in practice, include dozens of backside connections (e.g., vias 113 with conductive material 118 and leads 119).
As illustrated in FIG. 1C, at least some of the vias 113- and the conductive material 118 deposited therein—are misaligned relative to the conductors 115 in interconnect structure 114. This misalignment between vias 113 and conductors 115 results from a lack of precise alignment during formation of the vias 113. Due to the opaqueness of wafer substrate materials, as well as to equipment and process constraints, it is difficult to establish precise registration—and, hence, accurate alignment—between structures formed at the backside 111 of wafer 101 (e.g., vias 113) and structures formed on the wafer's opposing side (e.g., conductors 115 within interconnect structure 114). The misalignment between vias 113 and the conductors 115 of interconnect structure 114 may cause poor electrical connections to be formed between the conductors 115 and the conductive material 118 in vias 113, which can negatively affect device performance and lower production yields.